Google adds TPU 8i Max for big contexts, 8tx for secure data

Google announced two more eighth-generation TPU systems on November 9. TPU 8i Max puts two TPU 8i chips on one package for million-token contexts, and TPU 8tx keeps data and model weights protected in hardware even while they are being processed. Google says regulated teams can fine-tune, distill and run reinforcement learning on private data on 8tx “without needing to migrate sensitive data between separate clusters,” and every latency and density figure for both systems comes from Google’s own announcement.

What 8tx keeps encrypted

Data is normally encrypted when stored or sent over a network, but it has to be decrypted in memory while a processor works on it. TPU 8tx moves that protection into the hardware layer and keeps data and weights isolated while they are in use. It runs on the same silicon as TPU 8t, the training system Google introduced in April, paired with 5th Generation AMD EPYC host CPUs.

For speed, 8tx borrows Boardfly, the low-latency network Google built for TPU 8i. Google claims up to 2x lower latency than TPU 8t “with a near-zero performance penalty.”

Google is aiming 8tx at regulated enterprises and governments that run frontier or proprietary models and autonomous agents alongside their most sensitive data. It calls the system optimized for secure and confidential inference and “also great for small-scale training.” Testing Catalog described it as designed for large-scale training.

8i Max and the memory wall

When dozens of agents work across an entire codebase or hours of video at once, memory bandwidth becomes the bottleneck, Google says. TPU 8i Max combines two TPU 8i chips on a single package, which doubles the compute, the SRAM and the HBM bandwidth of a single 8i. The SRAM matters because TPU 8i uses that fast on-chip memory to serve low-latency token generation without a round trip to HBM, StackFutures reported.

Because the doubled silicon fits in the existing rack footprint, Google says data centers get significantly more compute per square foot and per watt.

Getting PyTorch onto it

TorchTPU, which Google open-sourced in October, runs PyTorch code and Hugging Face models natively on TPUs, and vLLM and SGLang come with TPU backends out of the box; Google’s phrase is “no code rewrites needed.” The agent suite that hooks TPU onboarding and kernel autotuning into Claude Code, Cursor and Google Antigravity is still in preview. On the memory side, Google is open-sourcing TPU Sync, which tiers KV caches (the attention state a model keeps for its context) off the chip into host DRAM and shared storage. Google claims it cuts KV transfer latency and time to first token by more than 90%.

Built on April’s chips

Google unveiled TPU 8t and TPU 8i at Cloud Next on April 22, the first time the TPU line split training and inference into separate silicon. At that point Google claimed up to 2.7 times better training performance for 8t and 80% better inference price-performance for 8i, each against the previous generation. StackFutures said both were open to preview requests at launch, with general availability expected later in 2026. TPU 8tx and TPU 8i Max are new system configurations built on that same silicon, and Google now counts nearly 100 TPU customers, including frontier labs, trading firms, retailers and universities.

Google says building systems around existing chips, rather than new chips, lets it deliver “specialized supercomputers in a matter of months rather than years.”