Fewer than 100 people built OpenAI's Jalapeño chip

A kernel benchmark that started at 0.31 percent of what the silicon could theoretically do reached 88.94 percent in about 40 hours, and the software that got it there came out of OpenAI's internal models. That is one piece of how OpenAI built Jalapeño, the accelerator it fully unveiled on 25 August, which IEEE Spectrum reports went from first architecture concept to first silicon in under 20 months.

At a glance

• OpenAI's hardware team averaged fewer than 100 people across the project and sits at about 100 now, a count that covers system design, software and supply chain but excludes Broadcom.
• Jalapeño does 13.4 petaflops of 4-bit compute with 232 gigabytes of memory at 15.4 terabytes per second, and OpenAI's benchmarks claim up to 3.6x lower end-to-end latency than Nvidia's GB300.
• The internal models fine-tuned for chip design were never named or released, Broadcom had access only to OpenAI's public models, and AI helped less on the backend, which Broadcom carried.

If you have not been following the hardware side of OpenAI: the project began in October 2024. Andrew Kahng, distinguished professor at UC San Diego, remembers Richard Ho as a keynote speaker at a 2016 IEEE Design Automation Futures workshop, where Ho already framed the time a chip takes as a function of how many iterations a team can run in a day. Chris Leary, who built the front-end flow around XLS, started XLS during his time at Google.

Jalapeño claims 3.6x lower end-to-end latency than Nvidia's GB300

The chip delivers up to 13.4 petaflops of 4-bit compute and reaches 232 gigabytes of the most advanced memory available at 15.4 terabytes per second. It is designed for pods of 2,048 chips. Benchmarks cited by OpenAI show end-to-end latency, prompt to last token, falling by up to 3.6x against Nvidia's GB300, at lower power.

The team behind it averaged fewer than 100 people over the project and stands at roughly 100 today, now working on second- and third-generation designs. Concept to first silicon took under 20 months, and only nine months separated the first RTL, the register-transfer level code that defines the chip's logic, from tapeout.

OpenAI owned end-to-end system design, including the inference accelerator, the memory hierarchy and the networking. Broadcom handled "physical design from the gates onward," says Ho. Kahng calls the pace "likely best in class today." Verkor.io co-founder David Chin says the schedule OpenAI gave is quite credible, but credits Broadcom: someone starting from scratch could not have done it.

Why did the front end run through XLS?

Because the models were better at software than at hardware. "We were thinking about how to leverage AI to make the project faster, and the AI was much better at software-looking things," says Leary, member of technical staff at OpenAI. "XLS in some ways looks like software, so it got that benefit."

XLS is an open-source high-level synthesis toolchain originally developed at Google. Engineers write in DSLX, a domain-specific language inspired by Rust, or in C++, and XLS converts that into Verilog, the hardware description language used to describe electronic systems. If you write Python and let a compiler worry about machine code, this is the same bargain one level down.

Ankur Srivastava of the University of Maryland points out that automation in chip design goes back decades. What LLMs add is an understanding of language and code, which suits the tasks that are "still in the linguistic domain of the problem." Kahng says high-level synthesis is more natural for a model to work with, and calls the workflow one that "has legs."

The project started on o3 and finished on pre-Astra models

Leary says the work began with help from models like o3, released publicly in April 2025 though available to the team earlier. By the end, the team had precursors to GPT-6 Astra, which did not reach the public until 3 September 2026. That newer model writes Verilog directly, with no trip through XLS, and is close to operating proprietary design tools on its own.

Ho confirmed the team also used internal LLMs fine-tuned for chip design that are not available to the public, and declined to detail them, adding that the Jalapeño team partnered with OpenAI's research group. The aim is to fold the lessons into the commercial models: "It's safe to say that Astra and following models will be very good at chip design," he says. Broadcom's team had access only to OpenAI's public, commercial models.

When first silicon came back in May, the team pointed its internal models at writing software to run benchmarks such as SemiAnalysis' InferenceX. On DeepSeek's multi-head latent attention kernel, performance climbed from 0.31 percent of the ceiling set by compute and memory bandwidth to 88.94 percent in roughly 40 hours. Ho says the result is repeatable, and schedule assumptions now build it in.

A 10 percent area cut on the matrix multiplication units

Much of the backend went to Broadcom: routing interconnects, closing and verifying clock and power, and sending the required design data to the foundry. OpenAI kept physical design engineers who work with their Broadcom counterparts on floorplan and routing. At IEEE Hot Chips 2026, Ho and Leary put a number on AI-guided physical optimization, a 10 percent area reduction for the matrix multiplication units measured against an optimized human baseline.

Verkor.io's Ravi Krishna calls OpenAI's backend approach a bit conservative and reads it as an artifact of when the work happened. Models from the last four to five months have improved, he says, with April 2026 onward the point where they began handling those tasks better. His co-founder Suresh Krishna says an agentic loop could largely accelerate the backend as well.

OpenAI's own framing admits the limit: whether these figures translate into real gains once Jalapeño is running across the inference fleet remains to be seen. The models that did much of the work are not named, and Chin's point stands that the timeline leaned on a partner who had done this before. In our view the 10 percent area figure is the hardest of the claims to check, since the human baseline it beats is described only as optimized.

What the second-generation flow adds

Ho says the next chip's workflow has "a lot of places" where AI is being introduced, naming verification and physical design. The team now has tools for automatic waveform manipulation and viewing, which identify the clock signals tied to failures and could speed up hardware debugging during design. Leary describes the second generation as a reset, a chance to trade safe choices for new ones. No timing for it has been given, and neither engineer expects chip design to become fully automated.